1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method having a CMP (Chemical Mechanical Polishing) process.
2. Description of the Related Art
Owing to recent demands for an increase in the operating speed of logic LSIs (Large Scale Integrated Circuits) or memories, much attention has been paid to a buried wiring structure as a method of forming a wiring structure using a chemical mechanical polishing process (CMP). A wiring material is, for example, Al, Cu, or W. In particular, Cu is gathering much attention because this material has a lower resistance and a high melting point. The formation of the buried wiring structure using Cu makes it difficult to use RIE (Reactive Ion Etching) because it requires that each of wiring layers must be surrounded by a barrier metal in order to prevent the diffusion of Cu. For these and other reasons, with this method, it is essential to employ the CMP process.
FIGS. 10A and 10B show a forming method for a buried wiring structure having, for example, a fine line-like pattern according to the prior art. As shown in FIG. 10A, an insulating film 102 having a plurality of grooves 102a is formed on a silicon substrate 101. TaN is deposited over the substrate by sputtering to form a TaN liner film 103 as a barrier metal. Subsequently, Cu is deposited by sputtering and plating to form a Cu film 104 composed of a Cu seed film and a Cu wiring film. When the Cu is deposited, it must be buried in the grooves 102a having the fine line-like pattern. Accordingly, an additive is added to facilitate the deposition of the Cu.
Then, as shown in FIG. 10B, the CMP process is used to remove an unwanted part of the Cu film 104 formed outside the grooves 102a. A polishing condition is properly selected including a polishing liquid, a flow rate of the polishing liquid, a polishing pad, a polishing load, a top ring revolution speed, and a turn table revolution speed.
Subsequently, the CMP process is used to remove unwanted parts of the TaN liner film 103 (this is not shown). The polishing condition is properly selected including the polishing liquid, the flow rate of the polishing liquid, the polishing pad, the polishing load, the top ring revolution speed, and the turn table revolution speed. In this manner, the buried wiring structure is formed which has a fine line-like pattern.
FIGS. 11A and 11B show a method of forming a buried wiring structure such as an upper wiring layer of a multilayer wiring structure which has a deep depth pattern, according to the prior art. As shown in FIG. 11A, an insulating film 112 having a deep groove 112a is formed on a silicon substrate 111. TaN is deposited over the substrate by sputtering to form a TaN liner film 113 as a barrier metal. Subsequently, Cu is deposited by sputtering and plating to form a Cu film 114 composed of a Cu seed film and a Cu wiring film. When the Cu is deposited, it must be buried in the groove 112a having the deep pattern. Accordingly, the Cu film 114 must be formed to be thick to some degree, for example, as a margin for the plating method.
Then, as shown in FIG. 11B, the CMP process is used to remove an unwanted part of the Cu film 114 formed outside the groove 112a. The polishing condition is properly selected including the polishing liquid, the flow rate of the polishing liquid, the polishing pad, the polishing load, the top ring revolution speed, and the turn table revolution speed.
Subsequently, the CMP process is used to remove the unwanted part of the TaN liner film 113 and others (this is not shown). The polishing condition is properly selected including the polishing liquid, the flow rate of the polishing liquid, the polishing pad, the polishing load, the top ring revolution speed, and the turn table revolution speed. In this manner, it is possible to form a buried wiring structure such as an upper wiring layer of a multilayer wiring structure which has a deep pattern.
For example, in the buried wiring structure formed in the grooves having the fine line-like pattern, the additive added for forming the Cu film by plating raises this Cu film to form an overplating portion. If it is assumed that a thickness of the Cu film formed on the upper portion of each groove is about 600 nm and that a polishing rate is about 1 μm/min, a polishing operation can be achieved in about 60 seconds. However, actually, it takes additional time to polish the raised overplating portion. Thus, an increased overpolish time must be set. This may degrade the in-plane uniformity of a wafer.
Furthermore, the additive used to deposit the Cu film is often distributed in a surface portion thereof at a high density. This additive is similar to an oxidation inhibitor and may adhere to the polishing pad or react chemically with the polishing liquid to make the polishing rate unstable. Moreover, even by setting an increased overpolish time, the unwanted part of the Cu film cannot be sufficiently removed.
Furthermore, for example, in the buried wiring layers formed in the grooves having the deep pattern, the Cu film must be formed thickly to some degree, for example, as a margin for the plating method. Consequently, the unwanted part of the Cu film is formed thickly. If it is assumed that a thickness of the Cu film formed on the upper portion of each groove is about 2,100 nm and that the polishing rate is about 1 μm/min, a polishing operation can be achieved in about 180 seconds. However, actually, as the polishing is carried out for a long time, because of polishing residues adhered to the polishing pad or the remaining polishing liquid, the polishing rate may vary depending on a position on the wafer, the time required for polishing, and the number of wafers processed. As a result, the polishing rate may become unstable. Therefore, the polishing will actually require a much longer time.
When the polishing rate is thus unstable, it is difficult to carry out the polishing while maintaining the in-plane uniformity. This makes it necessary to carry-out the polishing for a further increased time. Thus, the overpolish time must be further increased. This may degrade the in-plane uniformity of the wafer.
FIG. 12 is a graph showing a variation in uniformity depending on the polishing time. The abscissa axis indicates a position on the wafer. The ordinate indicates a polishing rate. Reference character A denotes the uniformity of the polishing rate per 60 seconds when a polishing time is 120 seconds. Reference character B denotes the uniformity of the polishing rate when the polishing time is 60 seconds. This graph indicates that an increased polishing time makes the polishing rate unstable, thus making it difficult to carry out the polishing while maintaining the in-plane uniformity. Furthermore, the polishing rate varies depending on the position on the wafer. Consequently, overpolishing occurs in an intermediate area between a central area and a peripheral area of the wafer.